1. Field of the Invention
The invention relates to integrated circuit processing and, more particularly, to the patterning of interconnections on an integrated circuit.
2. Background of the Invention
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send or receive signals external to the chip. Popular types of interconnection include aluminum alloy interconnections and copper interconnections.
One significant difference between aluminum and copper interconnections is the rate of oxidation of the metals. Pure aluminum is oxidized to aluminum oxide in the presence of oxygen. However, aluminum has a fairly low diffusion coefficient for oxygen in aluminum oxide, such that as soon as the aluminum oxide is formed, the pure metal (Al) underneath the aluminum oxide layer does not react with oxygen. The reaction between aluminum and oxygen is described as a self-limiting oxidation reaction.
Copper oxidation, on the other hand, is not self limiting. In the presence of oxygen, pure copper will continue to oxidize until substantially all the copper is oxidized to a copper oxide. Thus, once a copper interconnection is formed and patterned, an additional step of adding a passivation layer, typically silicon nitride (Si3N4), is employed to protect the exposed interconnection material from air or moisture.
One process used to form interconnections, particularly copper interconnections is a damascene process. In a damascene process, a trench is cut in a dielectric and filled with copper to form the interconnection. A via may be in the dielectric beneath the trench with a conductive material in the via to couple the interconnection to underlying integrated circuit devices or underlying interconnections.
A photoresist is typically used over the dielectric to pattern a via or a trench or both in the dielectric for the interconnection. After patterning, the photoresist is removed. The photoresist is typically removed by an oxygen plasma (oxygen ashing). The oxygen used in the oxygen ashing step can react with an underlying copper interconnection and oxidize the interconnection. Accordingly, damascene processes typically employ a thin hard mask or barrier layer of Si3N4 directly over the copper interconnection to protect the copper from oxidation during oxygen ashing in the formation of a subsequent level interconnection. In general, the Si3N4 hard mask layer is very thin, for example, roughly 10% of the thickness of the dielectric layer. Thus, when, for example, the via is cut through the oxide by way of an etch, prior art processes require that the etch stops at the underlying Si3N4. When the trench is then formed in the dielectric above the via, prior art processes require that the etch not remove the Si3N4 exposed by the via. The ability to etch the via and trench and preserve Si3N4 requires great selectivity of the etchant such that the thin Si3N4 layer is not etched away.
What is needed is a process, particularly useful with damascene processes, that does not require unrealistic expectations of etch selectivity.
A method of forming an interconnection is disclosed. The method includes the steps of depositing a first masking material over a first conductive region of an integrated circuit substrate and depositing a dielectric material over the first masking material. A via is formed through the dielectric material to expose the first masking material and a second masking material is deposited in a portion of the via. A trench is formed in the dielectric material over a portion of the via and the second masking material is removed from the via. The via is then extended through the first masking material and a conductive material is deposited in the via.